Symbolic model checking for sequential circuit verification (bibtex)

by Jerry R. Burch and Edmund M. Clarke and David E. Long and Kenneth L. McMillan and David L. Dill

Reference:

Symbolic model checking for sequential circuit verification (Jerry R. Burch and Edmund M. Clarke and David E. Long and Kenneth L. McMillan and David L. Dill), In IEEE Trans. on CAD of Integrated Circuits and Systems, volume 13, 1994.

Bibtex Entry:

@article{DBLP:journals/tcad/BurchCLMD94,
  author    = {Jerry R. Burch and
               Edmund M. Clarke and
               David E. Long and
               Kenneth L. McMillan and
               David L. Dill},
  title     = {Symbolic model checking for sequential circuit verification},
  journal   = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems},
  volume    = {13},
  number    = {4},
  pages     = {401--424},
  year      = {1994},
  url       = {TCAD94.pdf},
  doi       = {10.1109/43.275352},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tcad/BurchCLMD94},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}